load - shift register in vhdl -

i trying take 18 bit parallel load , change 9 2 bit outputs using shift register in vhdl. have come following code unsure of if thinking correctly.

architecture rtl of x   signal two_shifter  : std_logic_vector(1 downto 0);  signal load_data    : std_logic;  signal shift_enable : std_logic;   begin   --parallel serial shifter--  shifter: process(clk, reset)  begin    if (reset = '1')       two_shifter <= "00";    elsif rising_edge(clk)      if (load_data = '1')          two_shifter <= data_in;      elsif (shift_enable = '1')          two_shifter <= '0' & two_shifter(1);      end if;    end if;  end process shifter;   output_reg: process(clk, reset)  begin  if (reset = '1')     data_out <= '0';  elsif rising_edge(clk)     data_out <= two_shifter(0);  end if;  end process output_reg;   --serial parallel shifter--  input_reg: process(clk, reset)  begin   if (reset = '1')     two_shifter <= "00";   elsif rising_edge(clk)     two_shifter <= two_shifter(1) & receive_data;   end if;  end process input_reg;  

i have two_shifter 2 bits wide , didnt make load_data anything. work still?