vhdl - reading the value of input when clk ='1' in the mid way of clk -

i know rising_edge(clk) , when clk'event , clk ='1'. guess detect edge. lets want read input when clk high , in mid way. guess able write want convey how can that? if not correct please explain. thanks

in testbench, or synthesisable real hardware?

assuming clock has period clk_period, declared like

constant clk_period : time := 100 ns;   -- 10 mhz clk <= not clk after  clk_period/2; 

you can write testbench code like

wait until rising_edge(clk); wait clk_period/4; value <= my_input; 

however not synthesisable. in real hardware need different approach. fpgas have clock generation modules (plls, dlls, dcms) allow generate phase shifted or inverted clocks, , can use such block accomplish task. more specific suggestions depend on actual fpga using, , whether have faster clocks available.

for example, given clk , clk_2x phase aligned (so each clk edge clk_2x rising edge) can use falling edge of clk_2x while clk high.

process(clk_2x) begin   -- capture data    if falling_edge(clk_2x)       if clk = '1'          temp <= data_in;       end if;    end if; end process;  process(clk) begin    -- resynch main clock domain    if rising_edge(clk)       value <= temp;    end if; end process; 

alternative approaches can involve clocking adc delayed, inverted or otherwise modified clocks, or using selectable delays in iobs on input data (delayed) data stable during clock edge.

this - without really good sim models of external parts, can quite tricky right in simulation, , needs thorough testing on actual hardware. have used phase controllable clocks external parts , mapped out range of phases worked before picking 1 phase or delay value production.