system verilog - How do I make use of multipliers to generate a simple adder? -

i'm trying synthesize altera circuit using few logic elements possible. also, embedded multipliers not count against logic elements, should using them. far circuit looks correct in terms of functionality. however, following module uses large amount of logic elements. uses 24 logic elements , i'm not sure why since should using 8 + couple of combinational gates case block.

i suspect adder i'm not 100% sure. if suspicion correct however, possible use multipliers simple adder?

module alu #(parameter n = 8) (     output logic [n-1:0] alu_res,     input [n-1:0] a,     input [n-1:0] b,     input [1:0] op,     input clk );         wire [7:0] dataa, datab; wire [15:0] result;  // instantiate embedded 8-bit signed multiplier mult mult8bit (.*);  // assign multiplier operands assign dataa = a; assign datab = b;  always_comb     unique case (op)         // lw         2'b00:  alu_res = 8'b0;         // add         2'b01:  alu_res = + b;         // mul         2'b10:  alu_res = result[2*n-2:n-1]; // fraction         // mov         2'b11:  alu_res = a;     endcase  endmodule 

your case statement generate 4 input mux op select uses minimum of 2 logic cells. since assigning 8-bit variable in case block require 2 logic elements each bit of output. therefore total logic elements 8*2 large mux , 8 adder giving 24 total.

i'm doing project won't give away how optimise this. tell both mux's , adder can implemented using multipliers, 8 @ most. said don't think architecture optimal multiplier implementation.