system verilog - Sequence item generating 'X' or unknown value -

i have started seq item on sequencer generate seq item random constraints item generated has many "x" values. reason behind this?

here code:

virtual task run_phase(uvm_phase phase); begin   uvm_test_done.raise_objection(this,"started sequence");   `uvm_info(get_type_name(),"inside run_phase of base test:\n", uvm_low)   fork     #10;     spi_m_seq.start(spi_env_inst.spi_master.spi_sequencer);      #300;   join   uvm_test_done.drop_objection(this,"sequence finished"); end endtask:run_phase 

the systemverilog lrm states constraint solve can handle 2-value logic. means x's have due uninitialized 4-state logic types in class. here's , example of mean:

package some_package;    class some_class;     rand logic[15:0] field1;          logic[15:0] field2;      function void print();       $display("field1 = %x", field1);       $display("field2 = %x", field2);     endfunction   endclass endpackage  module top;   import some_package::*;    initial begin     some_class my_obj = new();     my_obj.randomize();     my_obj.print();   end  endmodule 

in example above, both fields of type logic (4-state), field1 declared rand. means when my_obj randomized, field assigned constraint solver. value of field2 remain 16'bx (the initial value of 4-state types).