fpga - System C - Reading in data bus one bit at a time -

i have simple block written in system c takes in 2 10x10 arrays, , performs matrix multiplication on them produce 10x1 output. issue having these 10x10 arrays stored "doubles" data coming block large , space utilization on fpga board using large purposes.

how serially read in 1 bit per clock cycle of 10x10 arrays not trying push in 2 10x10 double arrays in 1 clock cycle?

how set testbench send in data?

currently in module have:

sc_in<double> in_0; double [10][10] input_0; void init_0(){     int i, j;     (i=0; i<10; i++){         for(j=0; j<10; j++){             input_0[i][j] = in_0.read();          }     } }      sc_method(init_0);         sensitive << in_0 << clock.pos(); 

and testbench runs follows:

    for(i=0; i<10; i++){         for(j=0; j<10; j++){             in_0 = j;             wait();         }     } 

these 2 snippets of code provide setting of data prior matrix multiplication. current code produces input_0 10x10 matrix holding 9's, i.e. last value of double loop in testbench. want 10x10 array each row {0 1 2 3 4 5 6 7 8 9}.

thanks.

in standard c++, there no method read i/o or memory 1 bit @ time.

most processors read "word" of bits @ once. 8, 16, 32 or 64 or maybe otherwise.

most fpga interfaces based on 8, 16 or 32 bit wide registers. makes wiring easier , pleases s/w people.

otherwise, have input amount of bits , bit manipulation tricks handle remaining bits.

for example, make array 16x16 bits , ignore remaining bits?

if want special number of bits, recommend using spi or i2c busses. can clock @ bit level , adjustable in data bitwidth.