msp430 - MSP540F5438A Clock Bringup -

i'm new msp430 , trying better understand clock bring-up process. current purpose i'm going take pmmcorev out of equation using 4 mhz mclk within 0-8 mhz range pmmcorev = 0.

will knowledgable these parts please check logic , assumptions:

when part boots xt1 selected fll reference , dcoclkdiv selected mclk input. divm 0 mclk source not divided.

when system boots crystal not yet stable i'm assuming ucs moves in fail-safe mode , uses refo (internal trimmed 32k) fll reference.

already i'm bit confused. if divided dco used mclk how assured fll stable? how core functioning @ all?

it seems me mclk should either vlo or refo until can bring things gracefully.

can clarify these details , steer me in right direction initialize these clocks?

thanks!

per comment, yes.

at startup dco clock - need modify ucsctl registers , wait oscillators settle , go.

here steps in general:

1. change vcore level in steps (if necessary - in case not)
2. enable xt1
3. configure drive strength
4. select clock sources mclk, smclk, , aclk , source division need do
5. allow xt1, xt2 , dco stablize checking fault flags.

your external crystal 4mhz - wanting use mclk directly? or angle use reference fll dco, , use dco mclk (to achieve higher mclk frequency)? core volatage need depends on whatever mclk frequency is, not external crystal's frequency. if wanting use mclk rate of higher 8mhz need consider stepping pmmcorev 01.

for convenience, here reference ucs registers slau208m. http://www.ti.com/lit/ug/slau208m/slau208m.pdf#page=172

based on op, think should following if want use xt1 mclk:

//1) enable xt1 - xt1 off default. may not need explicitly //   perform step. according pg. 162 in slau208m, xt1 //   enabled when select source 1 of clocks. //   being explicit! ucsctl6 &= ~xt1off //xt1off= 0x0001u  //2) clear xt1drive bits - may not necessary clear these bits //   explicitly, xt1's drive strength can reduced 0 w/ 4mhz //   crystal. default, b11, full scale, consume //   more power, result in quicker settling time. ucsctl6 &= ~xt1drive0; //xt1drive0 = 0x0040u ucsctl6 &= ~xt1drive1; //xt1drive1 = 0x0080u  //3) select xt1 clock source xt1. ucsctl4 defaults 0x44 @ //   power on - dcoclkdiv (b100). selm_xt1clk = b000. ucsctl4 &= selm__xt1clk; //selm__xt1clk = 0x0000u  //4) wait xt1 stabilize {    //explicitly clear xt1 low , high frequency fault flasg, xt2 fault flag,    //and dco fault flag. 0x0008u, 0x0002, 0x0004, 0x0001 respectively.    ucsctl7 &= ~(xt2offg + xt1lfoffg + xt1hfoffg + dcoffg);     //clear oscillator fault interrupt flag in special function interrupt    //flags register.    sfrifg1 &= ~ofifg; //0x0002u } while (sfrifg1&ofifg); //test see if oscillator fault flags asserted. 

i using iar systems, not sure if using ccs if definitions named differently. went ahead , typed out hex each of operands.

on msp4305438a not have bypass.

does answer question?

also, in op mention wanting use xt1 reference fll. accomplished using ucsctl3. selfref field want set b000 use xt1,

here's definitions msp4305438a header in iar:

#define selref0             (0x0010u)    /* fll reference clock select bit : 0 */ #define selref1             (0x0020u)    /* fll reference clock select bit : 1 */ #define selref2             (0x0040u)    /* fll reference clock select bit : 2 */